[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #21)
> imho moving is absolutely necessary if you want to have tree-reductions run
> quickly without needing a full-crossbar somewhere on the ALU output -> other
> ALU input path.

not the ISA-design-level's problem and therefore invalid.

> here, i define running quickly to mean not needing to delay extra clock
> cycles because you're running register values through a separate
> slow-but-general lane-crossing mechanism.

this is an architectural designers decision that should in absolutely
no way cause us with "ISA Design Hats" on to base our decisions on.

> basically, a tree-reduction only needs to move data in a few set inter-lane
> paths, but if you skip moving, then you need to be able to read from any
> high-index element when combining with lower index elements.

you are conflating architectural internals with the responsibility of ISA
designers.

the architectural designer may choose to spot the patterns of ADDs (or
whatever)
and insert the prerequisite MVs as micro-ops *at their discretion*

a FSM architecture (TestIssuer) has no problems of any kind

another architectural designer may have 12R8W register files
and therefore have no lanes of any kind.

another designer may have cyclic shift buffers which substitute for
full crossbars.

etc etc etc etc.

none of these architectural decisions have anything *at all* to do with
ISA-level design except inasmuch that they all have to be considered
(and to some extent "implementation advice hints" given)

second, bear in mind, that the schedule of ops is entirely deterministic
based on having read the predicate mask.  ops may be issued (scheduled)
and analysed long before actual execution takes place.

no MVs.

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