[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the crucial thing that's needed, to make this algorithm work, is that it
musn't include or depend on a "MV" instruction (even as a micro-coded op).

the trick that i did in FFT and DCT there to avoid the need for MVs
was to have an array-of-indices where the *indices* were altered
(swapped around) if you needed to perform a MV.  the actual "MV"
did *not* actually occur but instead because the index had been
altered, the next ADD/MUL/WHATEVER would use the [index-redirected]
element as one of its srces.

it will be... hair-raising but not insurmountable.  the only "problem"
being that if there is only one element (somewhere half-way down the
array), then no ADD/MUL/WHATEVER gets applied, and consequently the
result is effectively invalid because no data actually got "reduced".
if a MV was used then obviously that one element would be MVed down
into the lowest-element spot in the result.

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