[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=553

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|DEFERRED                    |RESOLVED
         Resolution|---                         |INVALID

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cloding as invalid. a future version of SVP64 on top of quad precision
instructions (excluding all packed simd instructions) is more appropriate
and is nothing to do with this invalid mapping concept.

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