[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> (In reply to Jacob Lifshay from comment #6)
> 
> > Because that assumption is baked into LLVM, probably spread throughout the
> > code, making it quite difficult to split out bit order as independent from
> > byte order, we will probably want to take the path of least resistance and
> > change SVP64 to have bitmasks be MSB0 in BE, and LSB0 in LE.
> 
> unfortunately, if i understand correctly, it is quite insane and deeply
> problematic to follow this assumption.  let's walk through an example:

no, it's just integer predicates that are bit-reversed. CR predicates are
already logically laid out as a vector of bits rather than an integer, so they
are already in vector element order and don't need reversing.

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