[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
the algorithm we'd want to use is based on the algorithm without indirection
through the vi table:
def reduce(vl, vec, pred):
    step = 1;
    while step < vl
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            other_pred = other < vl && pred[other];
            if pred[i] && other_pred
                vec[i] += vec[other];
            else if other_pred
                vec[i] = vec[other];
            pred[i] |= other_pred;
    # scalar result is now in vec[0]

idk why the version with vi was added to the wiki, but it destroys most of the
benefits of the above version. the above version specifically reduces in a tree
pattern where changes in vl/pred don't affect where in the tree add/copy are
performed, allowing a cpu to efficiently implement tree reduction without
needing a full crossbar on the alu inputs or outputs. when some part of pred is
0, it changes the adds to copies, but doesn't change the position or order any
other operations.

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