[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
me on github:
> turns out Arm's faddv instruction which does reduction uses a pattern like
> the current SimpleV and what I originally proposed in this thread
> (distance=1,2,4 from diagram) -- except that it only matches when the
> vector length is a power of 2.

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