[Libre-soc-isa] [Bug 986] New: SVP64 LD/ST format simplification

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=986

            Bug ID: 986
           Summary: SVP64 LD/ST format simplification
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

realisation after adding post-increment mode that LDST needs to be
redesigned:

* bit 0: post-increment
* bit 1: element-strided
* bit 2: Fault-First in LDST-Imm, SEA in LDST-Idx
* bit 3: dz
* bit 4: sz

this is a huge simplification but also removing modes that really
should be associated with Arithmetic/CRops, otherwise LDST becomes
CISC.

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