[Libre-soc-isa] [Bug 905] New: create EXT001 Scalar reg access

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=905

            Bug ID: 905
           Summary: create EXT001 Scalar reg access
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

use one of the 64 EXT001 areas to allow full access to all
scalar regs.  needs an entirely new type of EXTRA encoding
exclusively dedicated to scalar.  must be capable of reaching
CR0..CR127 even for 3-arg CR operations.
must be capable of reaching GPR0..127 and
FPR0..127 even for 4-arg ALU ops (fmadd, isel)

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