[Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Apr 24 19:32:31 BST 2022


--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #14)
> Replying to:

> because that's needed for bigint by word division:
> uint64_t n[n_size], d; // n has most-significant word in n[n_size - 1]
> uint64_t carry = 0;
> for(i = n_size; i > 0; i--)
> {
>     uint128_t v = ((uint128_t)carry << 64) | n[i - 1];
>     carry = v % d;
>     n[i - 1] = v / d;
> }

... oink.

argh argh damnit.  missed this.  that's going to put huge pressure on those
4 remaining VA-Form slots in EXT04.  how can that be justified to OPF ISA WG.

ok let me think it through.

* v is 128 bit constructed from 2 64-bit.
* output1 is modulo of divisor
* output2 is modulo of divisor

by careful selection the same RC trick applies as to bigmul (madded)

by carefull-er selection it can also do scalar 128/64 div and/or mod
which also makes it useful for Algorithm D.

if RC contains carry and RC=0 as well as RT=0 is allowed then
selection of whether it *only* performs div or only mod is

by having an astounding amount of options i think we have a justification
for this precious opcode space.

let's see... adapt to swap RA and RC to make it similar to madded,
add zero conditional checking...

    divrem2du rt, ra, rb, rc
    v = (rc << 64) | rb;
    d = ra; // copy first in case rt is ra
    if rt != 0  
        rt = UDIV(v, d);
    if RS != 0
        RS = UREM(v, d);

same types of modes:

* RS=RT+VL mode when EXTRA bit 8 is 0 (default for scalar)
* RS=RC    mode when EXTRA bit 8 is 1

damnit signalling when not to write the remainder is difficult because
RS is implicit and can be a source.  how about:

    if rt != ra 
        rt = UDIV(v, d);
    if RT != 0
        RS = UREM(v, d);

messy.  if there were not 4 slots remaining in the EXT04 VA-Form
i'd say use 1 bit to decide if mod is written, and use RT!=0 for div
result, but that takes the *entire* space if divrem2ds is added as well.

tough call.

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