[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #59 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #58)
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=b77c0164e6cc0d55af15da49d355b5addf9c3f05
> 
> Turned out to be a little logic puzzle to try to find the slickest way but
> difference made the difference.

ha! neat! i like it.

okaaay so with both mem and reg compare in place it should
be possible to decouple the Sim from HDL, run them
*separately* one after the other, collating a series of
states in each case, and compare the states *afterwards*.

this may waste time in some cases if one of them creates
the wrong answer immediately, but hey.

while i sort that out, can you do some basic (independent)
unit tests, some fake mem and regs, just blast the values
in explicitly to the HDLState and SimState, don't bother
running a Sim or HDL loop at all, and check they are equivalent?

the important ones are the @unittest.expectedFailure()
when a mem location is either missing or different,
and likewise a reg that is deliberately wrong.

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