[Libre-soc-isa] [Bug 699] New: Draft Release v0.1 of SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=699

            Bug ID: 699
           Summary: Draft Release v0.1 of SVP64
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

First Draft release of SVP64 Standard. Based conceotually on
an x86-like "REP-" Prefixing of the Scalar Power ISA v3.0B,
Draft SVP64 brings the Power ISA up-to-date with advanced
Supetcomputing Vector Processing capabilities suited to
High Performance Compute, 3D GPU, Video, Scientific
and traditional DSP Workloads. With over 3 years of
development of the Draft 0.1 Specification, Features include:

* 24 bit prefix format for 64 bit Vector operations
  that fits within the Power ISA v3.1 64 bit Prefix
  scheme
* Vector Lengths up to 64 elements
* Element-width Overrides (polymorphism) for both
  source and destination registers
* Sub-vectors (vec2/3/4) suited to 3D GPU workloads
  and Audio/Visual processing
* Single and Twin Predication (back-to-back VREDUCE
  VEXPAND)
* 4 different Mode variants: Arithmetic/Logical,
  CR ops, Branch-Conditional and LD/ST. Similar
  to Power ISA v3.1 MTRR/MLS Prefix types providing:
  - Arithmetic Saturation
  - Fail-First (Speculative LD/ST)
  - Data-dependent Fail-First
  - Deterministic Scalar and Parallel Reduction
    and Iteration
  - "Predicate-result" (result is dropped if CR Field
    test fails)
* REMAP Scheduling for arbitrary-sized Matrices, and
  triple loop DCT and FFT.
* Both Horizontal-First (Cray) and Vertical-First
  (Mitch Alsup MyISA 66000) Vectorisation Modes

http://libre-soc.org/openpower/sv/svp64

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