[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #52 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

https://libre-soc.org/irclog/%23libre-soc.2021-09-17.log.html#t2021-09-17T19:22:43

khlehman i was just about to try splitting out result-generation
in test_core.py into a list-of-states for HDL and a list-of-states
for ISACaller sim, and realised that memory-checking hasn't been
added yet.

                        # Memory check
                        yield from check_sim_memory(self, l0, sim, code)

could you tackle that next?  check_sim_memory, in soc's test_compunit.py,
is brain-dead-simple, 5 lines of code, but needs splitting out into 3
separate loops:

* one to obtain the memory from the HDL "mem" object
* one to obtain the memory from the simulator
* one to compare the results

now... the minor complication is, that if split, you don't necessarily
know the size of the simulator memory (you'll see by examining the
check_sim_memory function).

have a hunt around (in decoder/isa/mem.py as well) see if you can think
of a solution/workaround

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