[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #40 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #39)
> https://git.libre-soc.org/?p=soc.git;a=commit;
> h=8e4d86cf105f8ab790982c87c65bc52ea228fd90
> 
> Debating on best final resting place for the split.

dropped into openpower-isa openpower/test/stste.py

> Been looking into qemu and what is already there.

an "ExpectedState" is likely a simple thing to work
on whilst investigating that.

although, just call it from _check_regs()

so, in e.g. shiftrot test:

* create ExpectedState class (in new state.py file)
* establish an instance of ExpectedState with int regs
  equal to the things that are being done manually
  with self.AssertEqual right now
* call the check function at the end of the simulation

the two things to pass in, obviously: sim and expected

qemu is dog slow, this i suspect is a bug in pygdbmi

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