[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #16)
> https://git.libre-soc.org/?p=soc.git;a=commit;
> h=18aaa0d2de6945f93ff5bb80d3b64e8dce523e6c
> 
> hdl portion finished and compared results in test_core

that looks really good, it's starting to take shape.  a quick tip:
to turn any function into a generator, just add "yield" somewhere
in it. first line will do.  not "yield something", just one word,
"yield".

then, you can (actually, have to) then do "yield from sim.get_intregs()"
*exactly* like with HDL.

it's a bit of a kludge but the end-result is that the two functions
have the exact same use-characteristics... and oh look, that's the
definition of an API.

    class SimState:
       def get_intregs(srlf):
            yield # nothing
            self.intregs.append(...)

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