[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #5)
> Start of breaking out functionality of check_regs
> 
> https://git.libre-soc.org/?p=soc.git;a=commit;
> h=dff1ed6ba3b97ab23d67107d35574163f079793c

ok so on the face of it, this looks great.  however, digging a little
deeper:

1) generally, the functions that are called are placed _before_ those
   that call them.  also, PEP8 (which we follow, strictly), you put
   2 blank lines between functions and classes, and one space between
   function arguments.

   i've done the moving of functions, i leave you to sort this out:
   def compare_core_sim_regs(dut,regsim,regcore, code):
                                 ^space ^space

2) remember i said, "only do the simulation part first"?
   this is because the HDL part uses "yield", and when
   using "yield" you have to *chain* sub-functions by
   also doing "yield from".  that means you can't also
   use them to return a parameter (in this case, the list)

3) remember, also, i said, "make sure to run unit tests *before* committing".
   i did that, and got:

ERROR: run_all (soc.simple.test.test_runner.TestRunner)
[case_0_regression_unconditional]
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/lkcl/src/libresoc/soc/src/soc/simple/test/test_runner.py", line
298, in process
    yield from check_regs(self, sim, core, test, code)
  File "/home/lkcl/src/libresoc/soc/src/soc/simple/test/test_core.py", line
156, in check_regs
    compare_core_sim_regs(dut,simregs,intregs,code)
  File "/home/lkcl/src/libresoc/soc/src/soc/simple/test/test_core.py", line
237, in compare_core_sim_regs
    (i, repr(code), regsim, regcore))
TypeError: %x format: an integer is required, not Signal

which means that literally every single unit test for HDL is now broken.
hooray! :)

so, given quite how obtuse yield is, i've sorted it with this:

commit 4d76cc90de0dc9d97cd6f00a175194bccdde62a1 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Sep 7 22:37:06 2021 +0100

    fun fixing of get_core_hdl_regs, "yield from"

take a look and see what i did, there.  it's not the best solution, but
we can work incrementally.  i'll run the full test_issuer.py, to make
sure it's all good.


next, i leave it up to you if you want to proceed to making a couple
of classes which store intregs, or whether you want to proceed to doing CRs
in the same style: one function for HDL-crs, one function for SIM-crs

if you make a pair of classes which store intregs, it should be obvious
that:

1) they should both store intregs NOT one stores intregs the other stores
   simregs

2) they should both have the exact same function name get_intregs NOT
   one has a function named get_core_hdl_regs the other called get_sim_regs

3) the name of each class should be HDLState and SIMState or something
   that reflects the fact that one is HDL-related and the other is Sim-related

start to see how it pieces together? one incremental step at a time.

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