[Libre-soc-isa] [Bug 615] talk to binutils and gcc developers about acceptable sv assembly format

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=615

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> sv.add.vsv. 5, 10, 12
> sv.add.sss 120, 120, 121
> sv.ldu.vs 20, 8(23)

not keen on these as they separate out the vector-note from the register
numbers.  this makes it really hard to write assembly code (including hard to
write unit tests).

additionally when immediate fields (L, sh, mb) are involved it becomes horribly
confusing

also for LD/ST there is a notation for unit stride and element stride where it
is clear which one is which by marking the immediate-offset rather than the
register

   4.v(r3)

vs

   4(r3.v)

separating out svv to be part of the op is, well, if we're forced to, then
we're forced to.  the lack of clarity means it's definitely low on the list.

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