[Libre-soc-isa] [Bug 650] write rfc for OpenPower fpr <-> gpr moves/conversions

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jun 3 10:27:57 BST 2021


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> Finished initial draft:
> https://libre-soc.org/openpower/sv/int_fp_mv/

looks really good, Jacob.

comments: float-load-immediate.  hmm. i like it, the only issue
being it needs its own major opcode (or, a massive part of one).
the cost-benefit therefore had better be really, *really* good.

one possibility is that it's added as a 64-bit prefixed version,
where the constant is made full 32-bit, mostly from the prefix.

the other possibility is, i notice the constants have zero in
the last 4 bits, and yet still cover a pretty large useful range

fmvis f4, 0x800 # writes -0.0 to f4
fmvis f4, 0x3F8 # writes +1.0 to f4
fmvis f4, 0xBF8 # writes -1.0 to f4
fmvis f4, 0xBFC # writes -1.5 to f4
fmvis f4, 0x7FC # writes +qNaN to f4
fmvis f4, 0x7F8 # writes +Infinity to f4
fmvis f4, 0xFF8 # writes -Infinity to f4

12 bits dedicated to an immediate is still pretty large but with
there being only one destination this is doable:

    0-5   | 6-10 | 11-23 | 24-30 | 31
    Major | FRT  | UI    | XO    | Rc

this would then fit into one column of a Minor 19 (similar to addpcis)
with one bit spare (bit 24, set to either zero or 1)

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