[Libre-soc-isa] [Bug 572] elwidth and indirection: two vectors, one width

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=572

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
so, for `ld reg, imm(reg)`, the src elwidth specifies:
0 -- unit stride -- loads from reg + imm + load_size * element_index
1 -- strided with stride of imm -- loads from reg + imm * element_index
written: ld reg, (reg), stride=imm
2, 3 -- reserved -- maybe split imm bits between offset and stride?
written: ld reg, offset_imm(reg), stride=stride_imm

for `ld reg, (base_reg + index_reg)`, the src elwidth specifies the elwidth of
index_reg, base_reg is always 64-bit.

similarly for store.

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