[Libre-soc-isa] [Bug 572] New: elwidth and indirection: two vectors, one width

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=572

            Bug ID: 572
           Summary: elwidth and indirection: two vectors, one width
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: oliva at libre-soc.org
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

in store or load operations, it's unclear to me whether(/when?) elwidth (dest
or src, respectively) affects the use of the corresponding register operand,
and of the scalar or vector references by it.

to keep the question and the answer simpler, I'll make this specifically about
the ld instruction and elwidth_src, as bug 570 (it was mostly unrelated to the
main theme of that bug, so I guess I should have filed a separate bug to begin
with).  So consider:

  svp64 elwidth_src=<nondefault> ld rD.v, iOff(rS.[vs])

- the register specifying the address to be loaded from can be scalar or
vector.  it's not clear how the use of the address register and of the memory
location/s named in it relate with elwidth_src.  I suppose the question could
be rephrased as "[when] does the .[vs] (and other source-related parts of the
prefix) apply to the register [scalar/vector] proper, or to the memory
[scalar/vector] referenced by it/them?"

-- if the load address register is a vector, is it the case that:

--- elwidth_src specifies the address width, and we take consecutive
elwidth_src-wide addresses from the address vector, and load full dwords (or
elwidth[_dest]-sized objects?) from each such (extended) address?  (this
appears to be the case for the pseudo-code given under 4.4)

--- or does elwidth_src specify the width of each load, and we take consecutive
dword-wide addresses from the address vector for each elwidth_src-wide load?

-- if the load address register is a scalar, is it the case that:

--- elwidth_src specifies the width of each load, and we take consecutive
elwidth_src-wide elements starting from the address given by the full address
register?

--- or does elwidth_src narrow the address register, and we load full dwords
starting at that narrowed and re-widened address?

if it were up to me, I'd treat rS in ld as address-wide, vector or scalar, and
use elwidth_src to override exclusively the memory access, uniformly.  but I'm
not pushing for this, just asking what the intended (specified?) semantics is
supposed to be, and for that to be made clear in the specification.


A symmetrical question/request for clarification and (pointers to?)
documentation is implied WRT stores and elwidth[_dest]


I envision the possibility of additional cases and elaboration of the answer
when subvl>1.

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