[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> 
> > https://libre-soc.org/openpower/sv/cr_int_predication/
> 
> arrrg this is going to drive me nuts.
> 
> i need some urgent help verifying the section added to confirm that it is
> correct.
> 
> this is the area which took 4 MONTHs to track down bugs and required 3 weeks
> of investigation and help from Ben and Paul.

Umm, where you have:
CR{7-n} = CR[32+n*4:35+n*4]

Assuming the above CR bit numbers are in MSB0 form, I think that gets CR
registers reversed:

The spec says the following (OpenPower ISA v3.1 section 2.3.1):
For all fixed-point instructions in which Rc=1, and for
addic., andi., and andis., the first three bits of CR Field
0 (bits 32:34 of the Condition Register)

You have mistakenly put CR7 in bits 32:34

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