[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #0)


> Even with implicit byte-reversal on load, this won't bit-reverse, 

we are not going to change OpenPOWER v3.0B scalar behaviour.

the perspective that IBM defined Scalar v3.0B Integer registers to behave
differently when a Logical operation (AND) is performed vs an ALU operation
(ADD) depending on whether LE or BE is set is just not how it works, and if we
try to do that it will make understanding and acceptance impossible.

the user must use the correct LD operation - ldbrx or ld - and the user must
expect that the ordering of bits follows the v3.0B defined conventions.

we are NOT going to add in implicit bytereversal that changes v3.0B Scalar
behaviour (explicit, maybe, implicit absolutely not)

everything will follow from that inviolate hard rule.

this will be challenging due to IBM's use of MSB0 conventions, even harder when
it comes to CR numbering, but tough luck for us: we deal with it.  sigh

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