[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #100 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #97)

> Well, all the above would be resolved if we treated scalar arguments as
> referring to the whole register, not just one element in a register, as I
> proposed (and originally assumed was the case).

i explained why that would compromise SV.

the cases that need a full walkthrough to understand why explicit control is
needed not implicit context-sensitive reversal are the interactions on:

* v3.0b ld
* v3.0b lw
* v3.0b st
* v3.0b stw
* v3.0b add (purely as an example)
* SV ld VL=1
* SV lw VL=1
* SV st VL=1
* SV stw VL=1
* SV add VL=1
* SV ld elwidth=32,destew=32 VL=1
* SV lw elwidth=32,destew=32 VL=1
* SV st elwidth=32,destew=32 VL=1
* SV stw elwidth=32,destew=32 VL=1
* SV add elwidth=32,destew=32 VL=1
* SV ld destew=32 VL=1
* SV lw destew=32 VL=1
* SV st destew=32 VL=1
* SV stw destew=32 VL=1
* SV add destew=32 VL=1
* SV ld elwidth=32 VL=1
* SV lw elwidth=32 VL=1
* SV st elwidth=32 VL=1
* SV stw elwidth=32 VL=1
* SV add elwidth=32 VL=1

and then VL=2 or 3 or 4.

the interaction on all of those - all permutations (all 55 of them) needs to be
thought through, every single one.

the sheer scope of that should give you some idea as to why, when we are a year
behind, i have been requesting again and again that we stop trying to get more
of these deep-dive features into SV.

periphery ones that go in a tiny portion of the spec and use an existing bit of
hardware (the 1<<r3 idea), no problem.

full-on fundamental redesigns of the regfile like this have to stop.

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