[Libre-soc-isa] [Bug 568] New: missing setvl/setvli behavior textual description of behavior

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=568

            Bug ID: 568
           Summary: missing setvl/setvli behavior textual description of
                    behavior
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: oliva at libre-soc.org
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

https://libre-soc.org/openpower/sv/setvl/ specifies the behavior only in
pseudocode.

It would be desirable if it the textual description stated that:

- MAXVL gets set to the requested value, always, as in, the immediate
represents all 64 possibilities, from 1 to 64, and the hardware *must* support
all of them, it can't actually set MAXVL to a value other than the requested
one

- VL gets set to MIN(reqVL, reqMAXVL), and never less than that.  I'd got the
idea from simple-v specs and from the examples on the page above that it could
be less, and this was making it harder to model the svp64 insns in the compiler


The first example is clearly copied from simple-v, since a0 and a3 are not ppc
register names.


I suppose NNNNN in 2. Format is the extended opcode, so far unspecified.  It
might be good to state this as well.

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