[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #98 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #97)
> Well, all the above would be resolved if we treated scalar arguments as
> referring to the whole register, not just one element in a register, as I
> proposed (and originally assumed was the case). Scalar here means register
> field marked scalar and subvl=1, it depends *only* on the bits in the svp64
> prefix, not on VL or mask or anything else that's dynamically adjustable.

It's the *combination* of scalar args meaning use the whole register *combined
with* registers being kept in the cpu's current endian mode.

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