[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #93 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #92)

> > multiplied up to 4 operands (src123 and dest) and 50 FUs this is 100,000
> > gates.
> 
> Are you calculating based on 4 muxes per FU or 4 muxes per pipeline?

tired.  supposed to be per pipeline, however the numbers on those when doing
4-lane vectors (regs banked modulo 4) for anything above regnum r31 it gets
pretty mental.

basically 4 lanes plus scalar, all pipeline QTYies are multiplied by 5.  which
means 5 lots of FMACs, probably 10 lots of Logical, 10 of ALU and so on.

nuts, eh? bit of overkill involved here given we were only aiming for 6 GFLOPs
initially.  this will be more along the lines of... mmm.... 120.  1.5 ghz times
2 (FP32 SIMD) times 2 (MAC) times 5 (5 FPUs) times 4 (SMP cores).

whoops.  might run a bit hot, there

the other option: 12R8W regfiles.  we ain't doing that.

-- 
You are receiving this mail because:
You are on the CC list for the bug.