[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |DEFERRED
         Resolution|INVALID                     |---

--- Comment #91 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
rright.  ok.  i took a look at the byteswap diagram: the PartitionedMul not
doing arbitrary permutations throws a royal spanner in the works, and we can't
spend 2 months fixing that.  so we go with the flow.

with arbitrary permutations out, the "aligned" byteswapping is ok.  the gate
count of 4-in MUXes looks to be around 8 (possibly less) which times 64 is
around 512 gates.

multiplied up to 4 operands (src123 and dest) and 50 FUs this is 100,000 gates.

this is just about borderline tolerable.

i am therefore de-marking this as invalid and instead putting it as deferred. 
if we have time (or if it proves to be so heavy a penalty elsewhere not to have
it), it goes in.

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