[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #88 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #86)

> I'll create some illustrations today.

this will help.

> > now i have written them out those are the same thing.  i thought that one of
> > them might involve moing the dynamic byteswapping to be part of
> > MultiCompUnit, where the quantity of gates gets multiplied even more than it
> > already is.
> 
> The byte-swapping would be a pipeline stage right after the mux for
> selecting which FUs to execute,

there are going to be at least QTY 50 (fifty) 64 bit regfile ports, each
crossbar being around 2k gates that's 100,000 gates if placed at the regfile
ports.

there are going to be around... 60 to 80 FUs (most of those "laned") which
means around 4x60 64 bit src operands plus another 60 dest ports.  5x60 = 300
operand ports.

this cost in gates, being now not at every regfile port but at every operand
port, is almost an order of magnitude larger.

300 x 2000 is... 600,000 gates in byte-reversal crossbars.

it's now of the order of 600,000 gates if placed at the source and dest
operands in each pipeline.

we are *not* doing this.

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