[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #83 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #80)
> > can you read VHDL?
> 
> I had never tried before this interaction.   I've had no trouble whatsoever
> figuring it out.  It's very readable.  I can probably even write it
> sensibly, given a body of code to refer to to pick up the constructs from.

yes, it's very readable and clear, it took me 6 months to go through this same
derivation process.  the microwatt team's expertise also shows in that they
provide useful comments.


> What I couldn't find, unsurprisingly, was specification of endianness of
> integers.

ah this will be in the VHDL spec.  readers are assumed to know it.  from what i
can gather/infer most HDLs perform arithmetic in LSB0 order, i.e. if performing
addition the carry out from bit N goes into the input of N+1

however, not having read the spec, this LSB0 arithmetic meaning *may* be
precisely because they use "downto".  however given that they do not use "upto"
anywhere it is a nonissue.

(aside: this "meaning" of arithmetic in the HDL as it propagates through layer
after layer is fundamentally where the decision to make the regfile LE stems
from)

> I couldn't find definitions for directions such as left and right, up and
> down, forward and backward either, or colors, either.  Just as expected.

it's part of the language, expected to be implicitly understood.

i did a quick search "VHDL endianness" and came up with this:

https://insights.sigasi.com/tech/to-downto-ranges-vhdl/

that explains clearly what "downto" means. took me a while to absorb.

it is unfortunately the precise inverted opposite of how nmigen Cat() works.
sigh.  but Cat() follows python argument ordering (*args), so hey what can you
do.

fortunately the microwatt developers chose not to include "upto" which means we
don't need to think of the underlying arithmetic as being BE or MSB0, only LE
and LSB0.

which is why i picked it for an illustration.

so.

does that help, with those definitions at the VHDL language level, to
understand the 4 combinations?  those are at comment #46 and comment #49.

i'll paste the relevant sections here:

  lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);

this is the setup of the LDST module.  those are single bits so no discussion
of ordering needed.

e_in.byte_reverse came from the Power Decoder, i'll paraphrase it from
decode1.vhdl:

    Byte Reverse     Opcode
    0                ld
    1                ldbrx

you can check that in decode1.vhdl

this then is where the table comes from:

* ld LE=1 XNOR BR=0    lv.byte_reverse=0
* ld LE=0 XNOR BR=1    lv.byte_reverse=1
  (LE=0 means BE mode)

and for ldbrx:

* ldbrx LE=1 XNOR BR=0 lv.byte_reverse=1
* ldbrx LE=0 XNOR BR=1 lv.byte_reverse=0
  (LE=0 means BE mode)

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