[Libre-soc-isa] [Bug 567] Allow transparent scalar loads and stores to/from registers allocated as vectors

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=567

Alexandre Oliva <oliva at libre-soc.org> changed:

           What    |Removed                     |Added
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                 CC|                            |oliva at libre-soc.org

--- Comment #1 from Alexandre Oliva <oliva at libre-soc.org> ---
My recommendation doesn't involve changing loads or stores in any way.

My recommendation is that the svp64 iteration over sub-register vector elements
obeys the in-memory array/vector layout.  I.e., if you load a vector with
smaller-than-64-bit elements into a register with a dword load, and iterate
over them with svp64, you visit them in the same order you would if iterating
over array elements in memory, and in the same order you would if the register
held a struct with an array, and you iterated over the elements in it.

This means that while in data LE mode the iteration goes as you wrote under
"One choice is", whereas in data BE mode the iteration goes as you wrote under
"Another choice is".

Not doing so would impose significant delays and risks of subtle errors onto
the compiler.

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