[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #82 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #81)
> Yes, however, what happens if you only issue the same-sized elements to any
> one ALU each cycle:
> 8 8 8 8 8 8 8 8
> 16 16 16 16
> 32 32
> 64
> but not:
> 8 8 16 32
> or other non-uniform combinations.
> 
> At that point, the 5-input mux is sufficient (actually, only 4-inputs
> needed), since there's one input for not byte swapped, 1 for 16-bit
> byte-swapped, 1 for 32-bit byte-swapped, and 1 for 64-bit byte-swapped.

Actually, if the 64-bit mux is instead partitioned into 8 8-bit muxes, we might
be able to still support arbitrary combinations of 8/16/32/64-bit together, as
long as elements are naturally aligned (16-bit is aligned to 16-bits, 32-bit is
aligned to 32-bits, and so on):
Assuming registers/data buses are dynamically swapped between BE/LE depending
on CPU data endian:
vector elements are still in the same order no matter their size, all that
happens with byteswapping is the bytes within a element are swapped, no bytes
swap past the element's boundaries. Therefore, the 4-input mux should still
suffice since each individual byte can only be unswapped, 16-bit swapped,
32-bit swapped, or 64-bit swapped. no other combinations are supported/needed
since they are ruled out by the natural alignment requirements.

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