[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #67 from Alexandre Oliva <oliva at libre-soc.org> ---
and just in case you're unconvinced because for 8-bit vector elements there's
byte-reversing load, consider 16-bit and 32-bit vector elements, including
floating-point ones; there aren't hword- and word-reversing loads, are there?

yes, loading one element at a time would still work, but we're talking about
optimizing the code for better performance, abiding by the documented layouts,
and avoiding making things gratuitously harder for either endianness.

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