[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #59 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #58)
> I found a pretty good explanation of a similar issue on Arm NEON on
> big-endian:
> https://llvm.org/docs/BigEndianNEON.html

ahh, that's a really good article.  describes the problem well, illustrates
what bitcasting is (which i was too distracted by the confusion over ldbrx/ld
to understand), allows me to understand that NEON SIMD registers are exactly
the same as SV regfile layout (LE ordering), and provides a solution.

they don't *like* the solution (use LD1) but it is a solution.

trying to solve this one in hardware is just too much.  following the exact
same path as described there for NEON in LLVM will do the job without
introducing horrendous hardware cost and complexity.

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