[Libre-soc-isa] [Bug 599] New: Usage of LSB0 in EXTRA pseudo-code

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=599

            Bug ID: 599
           Summary: Usage of LSB0 in EXTRA pseudo-code
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: cestrauss at gmail.com
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

Consider the pseudo-code for register number augmentation:

https://libre-soc.org/openpower/sv/svp64/#index13h1

Accorting to the tables below, it seems that the bit for scalar/vector
selection in "spec" is intended to be its MSB.

So, in MSB0 notation, it should be spec[0], not spec[2].

The augmentation bits then are the two less significant, so it should be
spec[1:2], not spec[0:1].

In other words:

if extra3_mode:
    spec = EXTRA3
else:
    spec = EXTRA2 << 1 # same as EXTRA3, shifted
if spec[0]: # vector (MSB of spec)
     return (RA << 2) | spec[1:2]
else:         # scalar
     return (spec[1:2] << 5) | RA

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