[Libre-soc-isa] Draft SVP64 adding XLEN to pseudocode spec (defaults to 64)

[Luke Kenneth Casson Leighton]

with thanks to 3mdeb, we've begun the process of altering the pseudocode
used by Libre-SOC to be able to do element-width over-rides.  example:
https://libre-soc.org/openpower/isa/fixedarith/

bearing in mind this is actual fully-functional executable pseudocode
(as opposed to a "guide for implementors"), which is used in a simulator
with thousands of unit tests confirming it, we felt it was important to
use the pseudocode for SVP64 when the width of registers is over-ridden
to 32, 16, or 8-bit values.

we also felt that creating then maintaining four near-identical copies
of the pseudocode was completely insane.

we'd like to keep the changes to the bare minimum, however, ha ha,
"bare minimum" in this case means a massive global/search/replace

* "64" ==> XLEN
* "63" ==> XLEN-1
* "32" ==> XLEN/2
* "31" ==> (XLEN/2)-1

which can get quite tedious, and in some cases justifies creating
temporary variables in the pseudocode.

this is going to interfere somewhat with the (large number of)
bugreports for the v3.0B Specification that need to be submitted,
but is ultimately unavoidable.

we need to move forward on SVP64 and have been holding the
element width overrides back as long as practical, pending the
establishment of the ISA WG and associated communications
channels and tools.  can't delay any further, sorry.

l.

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