[Libre-soc-isa] [Bug 664] design SVP64 branch instructions (sv.bc)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=664

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
svstep mode looks like it is too "CISC-like".  although remarkably
similar to CTR auto-decrement, svstep auto-increment involves predicate
skipping as well as REMAP.  realistically this is too much, unfortunately.

currently implementing sv.bc in ISACaller, this is the first time that
CR fields have been involved.

it would have been much better to have started with sv.crand (etc)
before trying to do sv.bc because then the infrastructure for read/write
of CR Fields would already be in place.

realistically, the pseudocode needs to change from

   CR[BI+32]

to

    CRF(BI[0:2])[BI[3:4]

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