[Libre-soc-isa] [Bug 664] design SVP64 branch instructions (sv.bc)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=664

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
* design pretty much done
* added SVP64 24-bit RM decoder
* added sv_analysis to include bc and bclr SVP64 EXTRA modes

-- 
You are receiving this mail because:
You are on the CC list for the bug.