[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #90 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/sv/predication/

jacob i updated this page to include a number of ideas: i will add a couple
more for completeness (such as adding a new predicate register type and
associated instructions)

i included what i *think* you might mean by the chunked mask idea, please do
review what i wrote.

i also did an implementation analysis: unfortunately, the change-over between
when the underlying scalar int reg switches from chunked-mask to actual integer
is... exceedingly complex, particularly when combined with the (necessary)
regfile cacheing / virtualisation.

as always though we need to be thorough in the comparative analysis and
complete and document all ideas.

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