[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #87 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #38)

> Why would you ever need to handle exceptions in the middle of a cmp
> instruction?

coming back to this, re-reading: all ops that produce CRs (incl. Rc=1) fall
under the same question.  actually, all vector ops do, regardless of whether
the results are

* vector of 64 bit regs only (Rc=0)
* vector of CRs only (cmp etc)
* vector of tuples 64bitreg+CR (Rc=1)


long latency pipelines/FSMs (SIN, COS, CORDIC) times long VL could turn out to
be several thousand cycles which will definitely begin to interfere with
interrupt servicing.

to solve this i spent some considerable effort working out how to do reentrant
SV, which involves storing the current loop counter because it is effectively a
"sub Program Counter".  if i recall correctly i think i even named it "sub-PC".

it requires the rule that the elements must be "sequentially completed" i.e. if
you cancel element 3 then it is prohibited to allow 4 and above to hit the
regfile.

the sub PC on return continues from the last non-cancelled, non-completed
element.

this in combination with shadow cancellation gives the ability to drop
incomplete vector elements on the floor, service the interrupt, and return to
where things left off.

realistically you only do this for high priority interrupts (NMIs) because it's
quite expensive and disruptive to drop large amounts of in-flight results.

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