[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #69 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #53)

> which allows the equivalent of Cray-style vector instruction chaining. Then,
> since having that many columns (rows? icr) in the scheduling dependency
> matrix isn't good, 

i have a sneaking suspicion that we are going to need to do a "register cache".
 PRF-ARF style, except backwards.  normally PRF-ARF is done to give *more*
registers (internally) than is in the ISA (e.g. x86 only 16): we need *less*!

a register cache would allow us to not just reduce the number of DepMatrix
columns in FU-REGs, it would also allow us the chance to "tag" them and make no
distinction between FP and INT as far as ALUs and RSes are concerned.

bottom line is, don't worry too much about DM sizes.  we're not doing 128x30
(which is 250,000 gates), 128 regs x 30 Function Units, we're more likely
doing... mmmm... 48 x 30 or so.  just have to see how many actual in-flight ops
are needed.

i can't quite get my head round the fact that POWER10 can handle a THOUSAND
in-flight instructions.

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