[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #67 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #66)

> the problem is that all 4 bits in each CR field is written by a compare (the
> most common mask generating operation), effectively changing it to be only
> useful for 1 mask lane per CR field, since all other masks that could be
> stored in the CRs are overwritten.

tck, tck, *thinks*...

if the limit's 64 CRs (no reason why we should not have 128, and a case could
be made that, well, 128 int/fp regs therefore 128 CRs) they can be copied to
intregs (mfcr) and back (mtcr), and in many cases (applying esoteric bitmanip
ops) that's what would be needed anyway.

the question is, really: realistically what the heck are we doing VL at 64 for,
that would use up that many CRs?

give me a mo to go over the vector 8-bit mask idea

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