[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #65 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #64)

> [... stuff for me to analyse and think about...]

> Vectorized CRs still have a bunch of the above mess, because they aren't 1
> bit per lane. Also, they have a ISA-level limiting effect on large VLs
> because of quickly running out of the 64 CRs when you need multiple masks
> (common in non-trivial shaders).

yes and no: remember they're 4-bit.  so that's 64x4 bits worth of stuff that
can be used for vector masks = 256 bits.  if we run out of those we're doing
something wrong :)

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