[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #56)

> I meant that masks should be able to have some bits calculated and used by
> succeeding masked vector instructions before other bits have finished
> calculating -- 

bit of overlap: this is not a problem, at all.  the OoO engine doesn't care if
the ALUs are going to be used as predicates or as vector elements, it's all
scalar as far as it is concerned.

the only trick is to make sure that there are enough ALUs.  if we only allocate
say 2x FP64 ALUs or 2x SIMD-capable INT ALUs, expecting this to cope with
sustained 2x FP64 predicated vector ops or 2x 8xbyte SIMD ops that's not gonna
happen because we forgot to allocate the extra ALU needed to do the ANDing and
XORing (etc) scalar mask ops.

okok for FP it would be fine because FP is a totaly separate pipeline from INT
logical.

okok actually INT Logical is even totally separate from INT arithmetic pipeline

:)

but you get the general idea. to get contention we would need the logical ALUs
to be totally jammed with vector ops such that they fought for pipeline
resources with the (scalar) predicate mask gen ops.

under these circumstances we would simply... allocate more Logical pipelines
and increase the number of Logical RSes.

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