[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #54 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #52)
> (In reply to Jacob Lifshay from comment #51)
>
> > Other benefits of integer registers as masks:
> > load/store for spilling takes 1 instruction, not several. Also, takes waay
> > less memory.
> > All the fancy bit manipulation instructions operate directly on integer
> > registers: find highest/lowest set bit, popcount, shifts, rotates,
> > bit-cyclone, etc.
> 
> there are some additional crucial bitmanipulation instructions needed here,
> including one that propagates from the first 1 and stops at the next 1. 
> some of these are listed in RVV's "mask" opcodes, and they are essential for
> efficiently doing strncpy and other operations.
> 
> we can drop these in as "scalar bitmanip" where they will benefit scalar as
> well.
>
> [snip]
>
> it is also not hard to vectorise the tranfer operations between CRs and
> intregs, and if we allow transfer of Vectors of CRs into one scalar intreg
> (which is already what "mfcr" already does!) then we keep to existing
> PowerISA design concepts, have the benefits of VRs, yet can still transfer
> vectors of CR tests to an intreg and perform bitmanip operations, clz,
> popcount and many more on it, efficiently and effectively.

Here’s a link to the RVV bitmanip verilog reference code, its already on the
wiki’s resources page, but I think it’s useful to have inline here.
https://github.com/riscv/riscv-bitmanip/tree/master/verilog

(The rvv equivalents of bperm are in rvb_bextdep in case anyone is looking for
it)

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