[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
source:
https://www.phoronix.com/forums/forum/hardware/graphics-cards/1207878-libre-soc-still-persevering-to-be-a-hybrid-cpu-gpu-that-s-100-open-source?p=1213364#post1213364

I'm looking at this CR thing for a while now, digging into that bug report, and
the Power ISA specification, and not really getting any great ideas.

One really bad idea - Ignore the CR and add a byte of mask at the bottom of
each GPR. But of course the would make register spill/save a nighmare. Plus
doesn't really help with GT/LT/EQ.

One start to an idea was to expand the CR bit feild into byte feilds (plus
mask). Also seems more terrible the more I think of it. If you were only ever
doing 8x simd maybe.

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