[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
right. ok. idea.  predicates do need to be created, but (sticking with a
Power-like design principle) the cmps are in CRs. therefore, the logical way
(to also preserve vector-cmp-CR behaviour) is to have mfcr copy *multiple* bits
from a vector of CRs into the destination reg, to create a predicate mask.

that predicate mask can them be applied to subsequent vector ops (including
even CR ops such as crand, mfcr and mtcrf if we decide that's a good idea)

however... i probably don't mean mfcr, above :)  mfcr is designed to copy whole
CRs

https://libre-soc.org/openpower/isa/sprset/

setb? no, that one is designed to turn a CR (which just tested whether a result
was +ve -ve or 0) into integer +1 -1 or 0.


we want a *bit* of a CR.  vectorised-isel?

https://libre-soc.org/openpower/isa/fixedtrap/

that looks better, esp. with predication applied to it to stop forced-zeroing.

for i in range(VL):
 if predicatemode & INTPRED[i] == 0 skip
  if CR[BC+32+i*4]=1 then RT[i] <- (RA|0)
  else                    RT[i] <- (RB)

that i think jacob is "effectively" what you are suggesting (is that right?)
except it uses CRs as an intermediary to get there.

it has the advantage that BC in the isel instruction can specify the offset
which allows the appropriate CR bit to be selected.

this is the "equivalent" of the idea of using some of the SVPrefix bits to
choose LE/GT/EQ but not actually needing to use precious SVPtefix bits to do
so!

those could instead be used to specify:

* isel ordinary  scalar/vector RT mode
* isel "hey treat RT as a pred" mode
* multipliers on BC that allow it to reach the full 64 CRs.

reason for this last one: BC is only 5 bits (0-31) to select any one of 32 bita
of the scalar mode CR reg.

but vector CR to store 64 CRs needs 3 more bits added to BC because scalar mode
CR reg has only 8 CRs CR0-CR7.

we want vector CR0-CR63 whixh is 8x as many CRs ao we need 3 extra bits on BC.

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