[Libre-soc-isa] [Bug 529] scheme for supporting 16/48-bit instructions on PowerPC LE with full backward compatibility

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=529

--- Comment #10 from Alexandre Oliva <oliva at gnu.org> ---
Uhh, sorry, the comment above was really meant for bug 238.  I'll copy it
there.  There were elements of the proposal to use odd addresses that would be
relevant here, but that I haven't elaborated on.

Specifically, we could make that work for both BE and LE: in 32-bit mode, the
most significant byte (regardless of code endianness) is the one that might
hold the 8-bit nop-ish insn to switch to 16-bit mode, since that's where the
EXT bits are.

As for 16-bit mode, the 4n+1 address would be one of the two bytes of the insn
full-contained in the word, and 4n+2 would be the other, regardless of
endianness.

At 4n+3 addresses, we'd have to go for the least significant byte of the word
at 4n for the first half of the 16-bit insn, again the one holding the opcode,
so that we can tell whether it's a mode-switching nop or we are to fetch the
second half from the next word.

If we're using misaligned 32-bit addresses, again we ought to use the LSB half
of the lower-address word as the MSB of the insn, to recognize the opcode
(possibly an 8-bit nop), and the MSB half of the higher-address word for the
remaining bits of the 32-bit insn split across two words.

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