[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #110 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---


On 11/21/20, Cole Poirier <colepoirier at gmail.com> wrote:

> idea is to do the opposite of ARM vs thumb. The op codes in the compressed
> ISA extension will simply be duplicate versions of ones that exist in the
> 3.0B version of the OpenPowerISA,

correct

> and that the 16 bit instructions will be
> in the same stream and addresses as the 32 bit standard ones.

correct.  up to this point it is exactly as in RVC from RISCV.

therefore, up to this point, the exact same tooling techniques apply.

> There will be
> one instruction to indicate entrance into 16 bit instruction mode, one to
> exit back to normal 32 bit mode, one to execute *only* the next instruction
> in 32 but mode then return to 16 bit mode

this is the point at which things deviate from how it works with ARM and RVC.

as explained in the introduction section RVC is specifically designed from the
groubd up with RVC in mind.  3 2bit tags are used in the LSBs as 16bit
identifiers; the 4th (0b11) is a Huffman escape sequence to indicate 32 bit
mode.

this technique pressurises the 32 bit mide by reducing available Major opcode
Space but that is another story.

to achieve the same thing for OpenPOWER we would need to take up something mad
like 24 Major Opcodes (anything and everything with 0b00/01/10 in the bottom 2
LSBs).

clearly that is flat-out unacceptable therefore the alternative is to use
"hidden context".

hidden context i.e. state aka "namespaces" aka ISAMUX aka ISANS aka
escape-sequencing basically has bits that come from a Special Purpose Register
(aka CSR) actually go directly into the instruction decoder as if it was
actually part of that instruction, because, well, in reality and in actual
fact, it is.

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