[Libre-soc-isa] [Bug 529] scheme for supporting 16/48-bit instructions on PowerPC LE with full backward compatibility

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=529

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
Basic idea: get around powerpc opcode being in 3rd byte by conceptually
swapping the order 16-bit halves of each 32-bit word are read from instruction
memory. Read bytes in the zero-based order:
2,3, 0,1,  6,7, 4,5,  10,11, 8,9,  ...

Diagram:
BE version:
bytes 0,1: 16-bit instruction -> executed 1st
bytes 2,3: msb 2-bytes of 32-bit instruction -+-> executed 2nd
bytes 4,5: lsb 2-bytes of 32-bit instruction -+
bytes 6,7: 16-bit instruction -> executed 3rd
bytes 8-11: 32-bit instruction -> executed 4th

LE version:
bytes 0,1: msb 2-bytes of 32-bit instruction --+
bytes 2,3: 16-bit instruction -> executed 1st +-> executed 2nd
bytes 4,5: 16-bit instruction -> executed 3rd |
bytes 6,7: lsb 2-bytes of 32-bit instruction --+
bytes 8-11: 32-bit instruction -> executed 4th

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