[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #33)
> Some very approximate statistics on how common bitcasting is in vector code:

appreciated.


> 31146*100%/2090019=1.49%
> Note that this is mostly LLVM's testsuite so likely not as representative of
> actual code.

understood.  it's a good start.

https://libre-soc.org/openpower/sv/fcvt/

that's going to take a while and need a few pages to go through.  however my
feeling is that it can be done as part of implementation: i.e. actually trying
to implement it and do the unit tests will require the coverage that in turn
will reveal patterns, from which a spec can be written.

the takeaway insight is that single precision opcodes are "half accuracy" ops
that allow intermingling of full accuracy ops without fcvts.  thus single
precision add on elwidth=32 means "do the op at FP16 accuracy then distribute
the bits across FP32 dest register in FP32 format".

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