[Libre-soc-isa] [Bug 564] add SV variant of fcvt to deal with elwidth differences in OpenPOWER FP scalar formats

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Dec 31 19:11:08 GMT 2020


--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
fmr p150 v3.0B 4.6.5

my feeling is that it would be reasonable to have these perform fcvt between
the src elwidth and dest elwidth, such that followup FP operations that were
also elwidth overridden had ("understood") the exact same FP format.

which brings us to an interesting point: what the heck does running
single-precision FP ops on elwidth=32 even mean??

single precision FP Ops on elwidth=default means "do the op @ FP32 but
distribute the bits across FP64"

my feeling is that this behaviour should be preserved at lower elwidth.

i.e. "do the op @ FP16 but distribute the bits across FP32".

i.e. single precision ops is redefined to be "do the op at half the precision"

fascinatingly if this is followed and the dest elwidth is *also* FP16 then
there is a way to get faster computation even when the src elwidth is FP32

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list